 | 500Mbps 2x2 MIMO Decoder |  |  |
 |  |  |  | | The area-efficient symbol detector is proposed for multiple-input multiple-output (MIMO) communication systems with two transmit and two receive antennas. The proposed symbol detector can support both……more |  | - Device : Xilinx Virtex-5 LX330 FF1760
- Maximum Operating Speed : 100 MHz
- Slices : 136857
- DSP48s : 104…more | | |  |  | | | | |
| 4-channel 64~2048-point FFT processor | | |
| | | | | The area-efficient FFT processor is proposed for MIMOOFDM ased SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 256, 512, 1024, 1536, and 2048-point, which ……more | | - 46.9-dB SQNR for data-path
- 90MHz clock frequency
- Slices : 26233
- DSP48s : 48
- Memory : 393.22Kbits…more | | | | | | | | | |
| 2.6W Class-D Audio Amplifier | | |
| | | | | This IP is a highly efficient filter-free class-D audio amplifier of delivering 2.6W of continuous average power to a 4Ω from 5.5V supply in a bridge tied load (BTL) with less than 1% THD+N. It pro……more | | - Supply voltage from 2.5V to 5.5V
- High efficiency up to 90%
- Under 3mA quiescent current
- 0.01% THD+N performance
- ……more | | | | |  | | | | |
| High Voltage ESD Protection Circuit using 3Stacked STNMOS in Dongb… | | |
| | | | | ESD protection circuit with Dongbu 0.35㎛ BCD process for an an I/O clamp. The circuit has effective ESD performance by using Stack technology in NMOS based Device. Also, the circuit has high holding……more | | - Process : Dongbu 0.35㎛ BCD Process.
- Voltage domain : 20V for I/O Clamp. 20V for Power Clamp
- Triggering voltage : 24.45V (@25℃)……more | | |  | | | | | |
| I/O & Power clamp ESD protection circuits using MPTSCR in Dongbu 0… | | |
| | | | | The High Voltage ESD protection circuit with Dong-bu 0.35㎛ BCD process is for an I/O clamp. The circuit has effective ESD performance by using Stack SCR structure. Also, the circuit has high holding……more | | - Process : Dongbu 0.35㎛ BCD Process
- Voltage domain : 1.8V for I/O and Power Clamp
- Triggering voltage : 5.64V
- High Hold……more | | | | | | | | | |
| High voltage ESD Protection Circuit using 4 Stacked SCR-based Stru… | | |
| | | | The high Voltage ESD protection circuit with TSMC 0.18㎛ CMOS process is for an analog/digital I/O circuit & Power clamp. The circuit has effective ESD performance by using stacked SCR structure.
more | | - Process : TSMC 0.18㎛ CMOS Process
- Voltage domain : 40V for I/O Clamp. 30V for Power Clamp
- Triggering voltage : 50.75V
- ……more | | | | | | | | | |
| High voltage ESD Protection Circuit using 2 Stacked SCR-based Stru… | | |
| | | | | High Voltage ESD protection circuit with TSMC 0.18㎛ CMOS process for an analog/digital I/O circuit & Power clamp. The circuit has effective ESD performance by using stacked SCR structure. Also, the ……more | | - Process : TSMC 0.18㎛ CMOS Process
- Voltage domain : 30V for I/O Clamp. 10V for Power Clamp
- Triggering voltage : 25.51V
- ……more | | | | | | | | | |
| High Voltage ESD Protection Circuit using 2Stacked HHVSCR in Dongb… | | |
| | | | | The datasheet present the High Voltage ESD protection circuit with Dong-bu 0.35㎛ CMOS process for an analog/digital I/O circuit & Power clamp. The circuit has effective ESD performance by using Stac……more | | - Process : Dong-bu 0.35㎛ BCD Process
- Voltage domain : 20V for Power Clamp
- Triggering voltage : 26.31V
- High Holding Volt……more | | | | | | | | | |
| High Voltage ESD Protection Circuit using 2Stacked STNMOS in Dongb… | | |
| | | | | ESD protection circuit with Dongbu 0.35㎛ BCD process for an an I/O clamp. The circuit has effective ESD performance by using Stack technology in NMOS based Device. Also, the circuit has high holding……more | | - Process : Dongbu 0.35㎛ BCD Process
- Voltage domain : 10V Power Clamp
- Triggering voltage : 15.1V
- High Holding Voltage :……more | | | | | | | | | |
| SCR-based ESD Protection device with high holding voltage in TSMC … | | |
| | | | | The ESD protection circuit with TSMC 0.13㎛ process for an analog/digital I/O & Power clamp. The circuit has effective ESD performance by using the extended p+ cathode to the first N-well and adding ……more | | - Process : TSMC 0.13㎛ Process
- Voltage domain : 3.3V - 5V for Power Clamp
- Low triggering voltage : 6.91V (@25℃)
- High Ho……more | | | | | | | | | |
| 2.6W Class-D Audio Amplifier | | |
| | | | | This IP is a highly efficient filter-free class-D audio amplifier of delivering 2.6W of continuous average power to a 4Ω from 5.5V supply in a bridge tied load (BTL) with less than 1% THD+N. It pro……more | | - Supply voltage from 2.5V to 5.5V
- High efficiency up to 90%
- Under 3mA quiescent current
- 0.01% THD+N performance
- ……more | | | | | | | | | |
| High Voltage ESD Protection Circuit using 3Stacked STNMOS in Dongb… | | |
| | | | | ESD protection circuit with Dongbu 0.35㎛ BCD process for an an I/O clamp. The circuit has effective ESD performance by using Stack technology in NMOS based Device. Also, the circuit has high holding……more | | - Process : Dongbu 0.35㎛ BCD Process.
- Voltage domain : 20V for I/O Clamp. 20V for Power Clamp
- Triggering voltage : 24.45V (@25℃)……more | | | | | | | | | |
| I/O & Power clamp ESD protection circuits using MPTSCR in Dongbu 0… | | |
| | | | | The High Voltage ESD protection circuit with Dong-bu 0.35㎛ BCD process is for an I/O clamp. The circuit has effective ESD performance by using Stack SCR structure. Also, the circuit has high holding……more | | - Process : Dongbu 0.35㎛ BCD Process
- Voltage domain : 1.8V for I/O and Power Clamp
- Triggering voltage : 5.64V
- High Hold……more | | | | | | | | | |
| High voltage ESD Protection Circuit using 4 Stacked SCR-based Stru… | | |
| | | | The high Voltage ESD protection circuit with TSMC 0.18㎛ CMOS process is for an analog/digital I/O circuit & Power clamp. The circuit has effective ESD performance by using stacked SCR structure.
more | | - Process : TSMC 0.18㎛ CMOS Process
- Voltage domain : 40V for I/O Clamp. 30V for Power Clamp
- Triggering voltage : 50.75V
- ……more | | | | | | | | | |
| High voltage ESD Protection Circuit using 2 Stacked SCR-based Stru… | | |
| | | | | High Voltage ESD protection circuit with TSMC 0.18㎛ CMOS process for an analog/digital I/O circuit & Power clamp. The circuit has effective ESD performance by using stacked SCR structure. Also, the ……more | | - Process : TSMC 0.18㎛ CMOS Process
- Voltage domain : 30V for I/O Clamp. 10V for Power Clamp
- Triggering voltage : 25.51V
- ……more | | | | | | | | | |
| High Voltage ESD Protection Circuit using 2Stacked HHVSCR in Dongb… | | |
| | | | | The datasheet present the High Voltage ESD protection circuit with Dong-bu 0.35㎛ CMOS process for an analog/digital I/O circuit & Power clamp. The circuit has effective ESD performance by using Stac……more | | - Process : Dong-bu 0.35㎛ BCD Process
- Voltage domain : 20V for Power Clamp
- Triggering voltage : 26.31V
- High Holding Volt……more | | | | | | | | | |
| High Voltage ESD Protection Circuit using 2Stacked STNMOS in Dongb… | | |
| | | | | ESD protection circuit with Dongbu 0.35㎛ BCD process for an an I/O clamp. The circuit has effective ESD performance by using Stack technology in NMOS based Device. Also, the circuit has high holding……more | | - Process : Dongbu 0.35㎛ BCD Process
- Voltage domain : 10V Power Clamp
- Triggering voltage : 15.1V
- High Holding Voltage :……more | | | | | | | | | |
| SCR-based ESD Protection device with high holding voltage in TSMC … | | |
| | | | | The ESD protection circuit with TSMC 0.13㎛ process for an analog/digital I/O & Power clamp. The circuit has effective ESD performance by using the extended p+ cathode to the first N-well and adding ……more | | - Process : TSMC 0.13㎛ Process
- Voltage domain : 3.3V - 5V for Power Clamp
- Low triggering voltage : 6.91V (@25℃)
- High Ho……more | | | | | | | | | |
| I/O & Power clamp ESD protection circuits using gate substrate tri… | | |
| | | | | The ESD protection circuit with Magna Chips 0.18㎛ CMOS process for an analog I/O and Power Clamp. The circuit has effective ESD performance by using gate/substrate trigger technique in NMOS based E……more | | - Process : Magna Chips 0.18㎛ CMOS Process
- Voltage domain : 3.3V - 5V for I/O Clamp
- Low triggering voltage : 7.78V
- High ……more | | | | | | | | | |
| I/O & Power clamp ESD protection circuit using floating body techn… | | |
| | | | | The ESD protection circuit with TSMC 65nm CMOS process for an analog/digital I/O circuit. The circuit has Effective ESD performance by using floating body technique in NMOS based ESD protection device……more | | - Process : TSMC 65nm CMOS Process
- Voltage domain : 1.8-3.3V for I/O & Power Clamp
- Triggering voltage : 4.45V
- High Holding ……more | | | | | | | | | |
| 500Mbps 2x2 MIMO Decoder | | |
| | | | | The area-efficient symbol detector is proposed for multiple-input multiple-output (MIMO) communication systems with two transmit and two receive antennas. The proposed symbol detector can support both……more | | - Device : Xilinx Virtex-5 LX330 FF1760
- Maximum Operating Speed : 100 MHz
- Slices : 136857
- DSP48s : 104…more | | | | | | | | | |
| 4-channel 64~2048-point FFT processor | | |
| | | | | The area-efficient FFT processor is proposed for MIMOOFDM ased SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 256, 512, 1024, 1536, and 2048-point, which ……more | | - 46.9-dB SQNR for data-path
- 90MHz clock frequency
- Slices : 26233
- DSP48s : 48
- Memory : 393.22Kbits…more | | | | | | | | | |
| 5.4Gbps Adaptive Equalizer | | |
| | | | | An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. ……more | | - Adaptive analog equalizer
- Unit-pulse charging technique
- Common mode tracking DAC
…more | | | | | | | | | |
| 2:1 Serializer for 7.5Gb/s transmitter | | |
| | | | | A 7.5Gb/s 2:1 serializer for 7.5Gb/s transmitter is designed in a 0.13um CMOS process. The proposed design is a 7.5Gb/s transmitter with bit-width calibration technique. To compensate the distortion o……more | | - 3-tap output driver for transmitter
- Duty-cycle correction
- 10:1 serializer…more | | | | | | | | | |
| 7.5Gb/s Referenceless Transceiver | | |
| | | | | A 7.5Gb/s referenceless transceiver for UHDTV is designed in a 0.13um CMOS process. By applying the dynamic pre-emphasis control and the handshaking clock generators, eye opening and jitter of the clo……more | | - Referenceless clock and data recovery circuit
- Handshaking clock generator
- Equalizer with pulse-width comparison
- 10:1 seri……more | | | | | | | | | |
| A 283.2uW 800Mbp/s/pin DLL-Based Data Self-Aligner for Through Sil… | | |
| | | | | A 283.2uW 800Mbp/s/pin DLL-Based Data Self-Aligner for Through Silicon Via (TSV) Interface is designed in a 0.13um CMOS process. The process skew among TSV-based stacked dies creates crucial problems ……more | | - Translatable align mode depending on condition
- Synchronous self align mode & self align mode
- Reduces the data confliction
…more | | | | | | | | | |
| MIPI DSI (Display Serial Interface) | | |
| | | | | This is a MIPI DSI IP which supports MIPI Alliance Specification D-PHY 1.0 complant PPI interface. It supports max 4 data lane & clock channel and function of error correction and CRC mode.…more | | - D-PHY interface
. MIPI Alliance Specification D-PHY 1.0 compliant PPI interface
- Number of Lane
. Max 4 data Lane & Clock ……more | | | | | | | | | |
| A 0.8-V 816-nW delta–sigma modulator for low-power biomedical | | |
| | | | | A distributed feedforward structure and bulk-driven operational transconductance amplifier are used in order to achieve efficient operation at a supply voltage of 0.8 V. Instead of conventional low-vo……more | | - 0.18-µm standard CMOS process
- 49-dB dynamic range
- Oversampling ratio: 20
- Sampling freqeuency: 10 kHz
- 0-250 Hz……more | | | | | | | | | |
| Fully synthesised decimation filter for delta-sigma A/D converters | | |
| | | | | Digital decimation filters are used in delta-sigma analogue-to-digital converters to reduce the oversampled data rate to the final Nyquist rate. This paper presents the design and implementation of a ……more | | - 0.25-µm 1P4M standard CMOS process
- 80-dB minimum stop-band attenuation
- Full-synthesized decimation filter
- Sampling fre……more | | | | | | | | | |
| A 0.6-V Delta–Sigma Modulator With Subthreshold-Leakage Suppress… | | |
| | | | A 0.6-V 34-μWdelta–sigma modulator implemented
by using a standard 0.13-μm complementary metal–oxide–semiconductor technology is presented. The input feedforward architecture is used ……more | | - 0.13-µm standard CMOS process
- 83-dB dynamic range
- Oversampling ratio: 48
- Sampling freqeuency: 1.92 MHz
- 0-20 k……more | | | | | | | | | |
