DDR SDRAM Memory Controller IP Code:KC004S0101
Description :
The DDR SDRAM controller interfaces between DDR SDRAM and user logic. It performs DDR SDRAM read and write access based on user requests. The DDR SDRAM transfer two bits of data for every data pin every clock cycle. Using DDR SDRAM effectively doubles the amount of data transferred for a given data bus width. For example, a DDR SDRAM system with 64 bits of data pin is equivalent to a single data rate (SDR) SDRAM of 128 bits of data. The DDR SDRAM CONTROLLER is a universal controller for DDR SDRAM memory systems. SDRAM timing such as row and column latency, precharge timing, and row access length are automatically handled by the SDRAM controller. All these timing parameters are set by the SDRAM controller on system reset and can be programmed by the user during run time to optimize system performance.
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