DDR2 PHY with Controller IP Code:KC094H0698
Description :
Double Data Rate 2 (DDR2) SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by DDR2 SDRAM devices. The core also performs all initialization, refresh and power-down functions. The core uses bank management modules to monitor the status of each SDRAM bank. Banks are only opened or closed when necessary, minimizing access delays. Up to 32 banks can be managed at one time.
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