MIPI D-PHY IP Code:KC183H0807
Description :
The MIPI D-PHY enables significant extension of the interface bandwidth for more advanced applications. The MIPI D-PHY configuration consists of a clock signal and data signals. To Address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to define and promote open standards for interfaces to mobile application processors. The MIPI D-PHY core is fully compliant with the D-PHY specification version 1.0. MIPI D-PHY describes a source synchronous, high speed, low power, low cost physical layer. The D-PHY solution is compliant with MIPI. D-PHY Transceiver unit is responsible for transmission and reception of data in High speed (HS) or Low Power (LP) mode. High speed mode is used for high-speed data transmission while the low power mode used for the control purpose. Point-to-Point lane interconnect can be used for either data or clock signal transmission. High speed receiver is a differential line receiver while low-power receiver is an un-terminated, single-ended receiver circuit. A single lane module is shown in the figure below.
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