4-port HDMI 1.4b/MHL2.0 receiver PHY&Link IP Code:KC553H0692
Description :
This IP is a 4 - port PHY and Link IP. It is composed of two major blocks. This IP is a PHY IP which receives HDMI and MHL serial data and transform into parallel data. This is a LINK IP which converts received parallel data into video format. This IP is capable of receiving 4 - HDMI or MHL ports. The selected HDMI/MHL port’s data is processed and transferred to the output ports in RGB or YCbCr format. This IP is based on the innovative archi- tecture to enable fast switching. This feature shortens the switching time during port change events. Especially in HDTV application with multiple HDMI inputs, this feature greatly improves cus- tomer experience. This IP has a built-in strong equalization circuit to amplify signals. This enable stable video processing even at highest frequency with poor cable environment. Also this PHY is based on an innovative clock and data recovery architecture which enables small size and power consumptions. The PHY requires two supplies. The 3.3V supply is mainly for HDMI termination. The 1.1V supply is used for most of the PHY operation. This PHY and LINK IPs are capable of handling UHD video data up to 30Hz frame rate. The LINK layer IP is composed of roughly 850k gate equivalent logic. The LINK processes de-serialized high speed data and inally generates RGB or YCbCr video data. Agile PHY control, video data processing including color space conversion, HDCP processing, video process and packet data processing and fast port switching functions are integrated into the LINK layer IP. The HDCP engine, deciphers encrypted HDCP en-abled video data and generates plain video and audio data. Video processing engine extracts video format, handles deep color and color space conversion. The audio engine extracts clean audio data to-gether with clean audio clock. The all digital audio engine generates clean audio clock without process and voltage dependence.
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